5 Innovative RISC-V Projects and Upcoming Events in 2024

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The RISC-V architecture, known for its open-source instruction set and flexibility, has sparked a revolution in the semiconductor industry. With its growing popularity, numerous innovative projects have emerged, showcasing the potential and versatility of RISC-V. Additionally, several key events have played pivotal roles in promoting and celebrating the advancements within the RISC-V community. In this article, we share 5 cutting-edge projects that are pushing the boundaries of what's possible with RISC-V, as well as highlight significant events that are shaping the future of this promising architecture.



Innovative Projects Centered on RISC-V

The World's First 32bit Homebrew CPU

There is a major CPU that is missing from the world. A 32bit homebrew CPU that implements a full and modern instruction set. The solution is to use 74' series logic chips and the RISC-V open source instruction set architecture. With a GNU toolchain already created for RISC-V it means we already have an assembler and compiler ready and waiting for our machine. So let's get rocking and create the ultimate in homebrew projects.



Join the project in creating the world's first 32-bit homebrew CPU using 74' series logic. For more information, please visit the link: https://hackaday.io/project/18491-worlds-first-32bit-homebrew-cpu


Pineapple ONE

32 bit RISC-V homemade CPU out of discrete components


"Max" clock speed: 500 kHz

Program memory: 512 kB

RAM size: 512 kB

VGA Output: 200x150 px (black and white)

2x 8-bit Input ports

2x 8-bit output ports

This is basically a "modern" CPU made out of hardware, that was available in the early days of semiconductors (This means that there is no FPGA or any microcontroller on board, apart from this, you could use whatever integrated circuits you could find). For more, you can visit: https://hackaday.io/project/178826-pineapple-one



The Cheapest RISC-V 64 Computer (by Now)

Want a piece of RISC-V hardware to play with, but are concerning with the price? Why not build one by yourself with a cost less than 10$!

"Open source ISA" surely is an attractive title to geeks. No doubt that the RISC-V would got so much attention, but its hardware is not yet very accessible. In the mid of this year, Chinese chip company Allwinner released their first RISC-V 64 SoC D1, with an evaluation board costs about 100$. If this price is not low enough for you, here is a SBC based on D1s, the newest SoC developed by Allwinner, with a total cost less than 10$!

Join the project in creating The Cheapest RISC-V 64 Computer. For more information, please visit the link: https://hackaday.io/project/182389-the-cheapest-risc-v-64-computer-by-now



The NEORV32 RISC-V Processor

The NEORV32 Processor is a customizable microcontroller-like SoC based on the NEORV32 RISC-V-compatible CPU.

It is intended as auxiliary processor within larger SoC designs or as stand-alone custom microcontroller. The processor provides common peripherals like GPIO, serial interfaces, timers and embedded memories. All features beyond the base CPU are optional and can be configured via VHDL generics.

The project comes with a complete software ecosystem that features core libraries for high-level usage of the provided functions and peripherals, application makefiles, a run-time environment, several example programs and even Zephyr and freeRTOS ports.

The project is intended to work "out of the box " - just synthesize the provided test setup, upload it to the FPGA board of choice and start tinkering. Check out the project's rationale if you want to know more.

The project is hosted on GitHub. The project's change log can be found here. Join our chat on out gitter channel.



fRISCy: FPGA + RISC-V Digital Processing Board

Currently, any work with an FPGA will require a proprietary toolchain. Recent advances from Project IceStorm now allow for full Verilog-to-bitstream using open source tools. Combine that with the open RISC-V ISA in the SiFive E310, as well as the SYZYGY open FPGA peripheral connector and you have a high performance platform full of open-source options!
fRISCy could be used in a myriad of ways. First, it can be used for benchtop development work. It would really shine as the central processing unit in a system with different peripherals. For example, it could form the base of a high-performance SDR, or it could be used at the heart of an industrial controls system.



fRISCy combines SiFive's new RISC-V microcontroller with a Lattice iCE40 FPGA for a platform that is all open 
source! Join it, please visit: https://hackaday.io/project/97218-friscy-fpga-risc-v-digital-processing-board


RISC-V Upcoming Events in 2024 
RISC-V Day Tokyo 2024 Winter

The RISC-V Day Tokyo conference is the largest RISC-V event in Japan. The RISC-V Day Tokyo 2024 Winter conference will be held on Tuesday, January 16, 2024 from 9:00-17:00 JST (UTC+9) at the Ito International Research Center, The University of Tokyo. We will bring together excellent RISC-V-related technologies and products, as well as key people and engineers, and provide business opportunities such as increasing product awareness, realizing collaboration between companies, technology exchange, and information gathering. For more, please visit: https://riscv.or.jp/en/risc-v-day-tokyo-2024-winter-en/.



HPC Asia 2024

RISC-V HPC/Datacenter has been accepted into HPC-Asia 2024 the Third RISC-V HPC Workshop on Jan 25-27 in Nagoya, Japan.



High performance computing (HPC) is a key technology to solve large problems in science, engineering, and business by utilizing computing power that has been continuously evolving. The International Conference on High Performance Computing in Asia-Pacific Region (HPC Asia) is an international conference series in the Asia Pacific region on HPC technologies, fostering exchange of ideas, research results and case studies related to all issues of high performance computing.
The 7th edition, HPC Asia 2024 will be held with the motto “Stepping forward to the Post Moore Era together.” Although we are now entering the Exascale era, the Post Moore era will soon follow, and HPC Asia 2024 will provide a unique opportunity to discuss the challenges towards the Post Moore era. In addition, we need to pay close attention to the integration of HPC and AI: while the “convergence” of HPC and AI has been broadly discussed, the intensive “integration” of those will be essential towards computing in the Post Moore era. 
For more details, please visit the event website. https://sighpc.ipsj.or.jp/HPCAsia2024/


FOSDEM 2024 RISC-V Devroom

FOSDEM is a free event for software developers to meet, share ideas and collaborate. Every year, thousands of developers of free and open source software from all over the world gather at the event in Brussels. This year it’ll be a RISC-V Devroom! The Devroom will be held on February 4, 2024 in Brussels, Belgium.
The full schedule is available at: https://fosdem.org/2024/schedule/track/risc-v-devroom/



The momentum behind RISC-V is undeniable. The innovative projects we've discussed illustrate just a glimpse of the architecture's capabilities, and the events mentioned are testament to the vibrant and engaged RISC-V community. As more organizations and developers embrace RISC-V, we can expect a continual stream of breakthroughs and collaborations that will propel the industry forward. 

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